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AS1123
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 17. Switching into Low-Current Diagnostic Mode Timing Diagram
Low-Current
Diagnosis Mode
OEN
t TESTING
LD
t SU(ERROR)
t GSW(ERROR)
Load Internal all 1s
Test Pattern
(optional)
t H(L)
CLK
t GSW(ERROR)
t SW(ERROR)
SDI
Re-entering Error Detection
Mode
SDO
T FLAG O FLAG S FLAG
t P1
Don’t
Care
(see Figure 15 on page 13)
(see Figure 16 on page 14)
Normal Operation Current
For detailed timing information see Timing Diagrams on page 8 .
V THH Level
Two different threshold levels of the error detection can be set via a bit. The bit can be entered via 4 clock pulses during error-detection mode. To
set level 2 (V THH is 80% of Vdd) a 0 must be placed at SDI after the rising edge of the 3rd clock pulse.
To set level 1 (V THH is 54% of Vdd) a 1 must be placed at SDI after the 3rd clock pulse. The level 1/level 2 information will be latched through if
multiple AS1123 devices are in a chain. At the rising edge of the 4th clock pulse the bit will be read out and the AS1123 is set to Level1 or Level2.
Figure 18. V THH Level Timing Diagram
OEN
LD
t SU(ERROR)
CLK
1 = Level1
SDI
0 = Levle2
1 = Level1
SDO
T FLAG
O FLAG
S FLAG
0 = Level2
t P4
t SU(D)
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